The present invention relates to methods of manufacturing semiconductor devices, and more particularly to a method of fabricating UMOS semiconductor devices using a self-aligned, reduced mask process.
The advantages and applications of MOSFET devices are well known, as are methods of fabricating such devices. Two variations of MOSFETs have become popular, the double-diffused MOS (DMOS) device and the trench-gated MOS (UMOS) device. As illustrated in FIG. 1, MOS devices (a DMOS MOS controlled thyristor, MCT, is shown) are horizontally disposed with surface gates. In contrast, UMOS devices, such as the UMOS MCT illustrated in FIG. 2, are vertically oriented and use trenched gates. As is apparent, UMOS devices reduce cell space requirements.
The efficient fabrication of UMOS devices and the ability to manufacture UMOS devices which meet anticipated performance have been problems which have affected their utility. For example, DMOS devices are adaptable to a variety of well-known surface channel and concentric diffusion manufacturing methodologies which cannot be used in UMOS devices, and UMOS devices do not lend themselves to self-aligned processes or to processes which reduce the number of masks as obviously as comparable DMOS processes. However, such processes would make UMOS devices a more attractive alternative to DMOS devices because of the improvements in manufacturing throughput, greater UIS capability, decreased alignment sensitivity, and lower specific on-resistance.
For further background, see the discussion of DMOS and UMOS devices in U.S. Pat. No. 5,488,236 issued to Baliga, et al. Jan. 30, 1996 and an example of UMOS fabrication in U.S. Pat. No. 5,360,746 issued to Terashima Nov. 1, 1994.
Accordingly, it is an object of the present invention to provide a novel method of fabricating semiconductor devices which obviates the problems of the prior art.
It is another object of the present invention to provide a novel method of fabricating semiconductor devices which uses self-aligned implants and a reduced mask set process.
It is yet another object of the present invention to provide a novel method of fabricating semiconductor devices which uses a blanket source implant and a high energy body implant before trench and mesa formation, and a shallow etch to form source and body contacts in the mesas.
It is still another object of the present invention to provide a novel method of fabricating semiconductor devices which uses a blanket source implant and a high energy body implant before trench and mesa formation, followed by redistribution of the implanted dopants so that the body region extends deeper into the substrate beneath the centers of the mesas than adjacent the walls of the trenches.
It is a further object of the present invention to provide a novel method of fabricating a UMOS semiconductor device which includes a blanket source implant, a high energy body implant, an etch through a hard mask to form trenches and mesas, concurrently providing a gate oxide on surfaces of the trenches and mesas and redistributing the dopants so that the body dopant concentration beneath the centers of the mesas extends deeper into the substrate than adjacent the walls of the trenches, and where the initial body implant may be a blanket implant or an implant through a mask which concentrates the dopant in the centers of the mesas.
It is yet a further object of the present invention to provide a novel method of fabricating a UMOS semiconductor device in which an N type (source) dopant is blanket implanted and a P type (body) dopant is blanket implanted at high energy into the surface of a substrate; the substrate is etched through a hard mask to form trenches and mesas; the two dopants are redistributed so that the P type dopant concentration beneath the centers of the mesas extends deeper into the substrate than adjacent the walls of the trenches, the mesas are etched through a further mask to form contact windows which expose portions of the source and body regions.
It is still a further object of the present invention to provide a novel method of fabricating a UMOS semiconductor device in which an N type (source) dopant is blanket implanted and a P type (body) dopant is implanted at high energy through a mask into the surface of a substrate, the mask having first openings for the trenches and second openings over the mesas which are narrower than the mesas; the substrate is etched through a hard mask to form trenches and mesas; the two dopants are redistributed so that the P type dopant concentration beneath the centers of the mesas extend deeper into the substrate than adjacent the walls of the trenches; the mesas are etched through a further mask to form contact windows which expose portions of the source and body regions.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.
In the following, first and second conductivity types are opposite conductivity types, such as N and P types. Each embodiment includes its complement as well. Note also that the figures herein illustrate vertical cross sections of devices and that the devices extend laterally (into and/or out of the page) in a manner appreciated by those of skill in the art.